1. Field of the Invention
The present invention relates to switching power supply circuitry. Specifically, the invention relates to DC-to-DC converters that include a switching controller or regulator (implemented as an integrated circuit), and circuitry (typically including a current sense resistor) external to the controller or regulator chip, with the controller or regulator chip including soft start circuitry but requiring no component external thereto (other than the conventional components present in DC-to-DC converters having no soft start capability) in order to accomplish a soft start.
2. Description of the Related Art
FIG. 1 is a conventional DC-to-DC converter which includes current mode switching controller 1 which is implemented as an integrated circuit, and boost converter circuitry external to controller chip 1. The boost converter circuitry comprises NMOS transistor N1 (which functions as a power switch), inductor L, current sense resistor R.sub.s, Schottky diode D, capacitor C.sub.out, feedback resistor divider R.sub.F1 and R.sub.F2, compensation resistor R.sub.c, and compensation capacitor C.sub.c, connected as shown. The FIG. 1 converter produces a regulated DC output voltage V.sub.out across load R.sub.o, in response to input DC voltage V.sub.in.
Controller chip 1 includes oscillator 2 (having a first output and a second output), comparator 8, driver 6 which produces an PATENT output potential V.sub.DR at pad 12 (to which the gate of switch N1 is coupled), latch 4 (having "set" terminal coupled to oscillator 2, "reset" terminal coupled to the output of comparator 8, and an output coupled to the input of driver 6), error amplifier 1 (having a non-inverting input maintained at bandgap reference potential V.sub.ref), and circuit 9 (having a first input coupled to the second output of oscillator 2, a second input coupled to pad 13, and an output coupled to the inverting input of comparator 8).
Pad 13 is at potential V.sub.c, which is determined by the output of error amplifier 10 (in turn determined by the difference between the instantaneous potential at Node A and the reference potential V.sub.ref) and the values of external resistor R.sub.c and capacitor C.sub.c. Reference potential V.sub.ref is set (in a well known manner) by circuitry within chip 1, and is normally not varied during use of the circuit. In order to set the regulated level of the output voltage V.sub.out, resistors R.sub.F1 and R.sub.F2 with the appropriate resistance ratio R.sub.F1 /R.sub.F 2 are employed.
Oscillator 2 asserts a clock pulse train (having fixed frequency and waveform as indicated) at its first output, and each positive-going leading pulse edge of this pulse train sets latch 4. Each time latch 4 is set, the potential V.sub.DR asserted by driver 6 to the gate of transistor N1 causes transistor N1 to turn on, which in turn causes current l.sub.L from the source of N1 to increase in ramped fashion (more specifically, the current l.sub.L increases as a ramp when transistor N1 is on, and is zero when transistor N1 is off. The current through diode D is zero when N1 is on, it increases sharply when N1 switches from on to off, then falls as a ramp while N1 is off, and then decreases sharply to zero when N1 switches from off to on). Although transistor N1 turns on at times in phase with th periodic clock pulse train, it turns off at times (which depend on the relation between reference potential R.sub.ref and the instantaneous potential at Node A) that have phase that is independent relative to that of the pulses of the periodic clock pulse train.
Oscillator 2 asserts ramped voltage V.sub.osc (which periodically increases at a fixed ramp rate and then decreases with a waveform as indicated) at its second output. Circuit 9 asserts the potential V.sub.c -V.sub.osc to the inverting input of comparator 8. Assertion of the potential V.sub.c -V.sub.osc (rather than V.sub.c) to comparator 8 is necessary for stability.
The non-inverting input of comparator 8 is at the feedback potential V.sub.s =l.sub.L R.sub.s, which increases in ramped fashion in response to each "set" of latch 4 by oscillator 2. When V.sub.s =V.sub.c -V.sub.osc (after latch 4 has been set), the output of comparator 8 resets latch 4, which in turn causes the potential V.sub.DR asserted by driver 6 to the gate of transistor N1 to turn off transistor N1. Thus, by he described use of both signals output from oscillator 2 and feedback asserted to error amplifier 10 from Node A, controller chip 1 switches transistor N1 on and off with timing that regulates the output potential V.sub.out of the FIG. 1 circuit.
However, the conventional circuit of FIG. 1 has an important disadvantage which exists because during "start up" of the FIG. 1 circuit, V.sub.out must rise from its initial value of O V (zero volts above ground) to its regulated value. Because V.sub.out typically is initially much lower than its regulated value, the duty cycle of switch N1 during start up can be very high. This situation can cause the inductor current to rise above its equilibrium value, and because the current in inductor L cannot change instantaneously, it can remain above its equilibrium value for a short time. This can cause the output voltage to rise above its regulated value. This excessive rise is commonly referred to as overshoot. Overshoot is a well understood phenomenon and most conventional switching controllers (including most conventional current mode switching controllers) employ some sort of soft start circuitry to reduce or eliminate overshoot.
Other conventional DC-to-DC converters which include a current mode switching controller implemented as an integrated circuit (as does the FIG. 1 circuit) also include circuitry (e.g., buck converter circuitry) other than boost converter circuitry that is external to the controller chip. For example, the conventional DC-to-DC converter of FIG. 2 includes controller chip 101, and buck controller circuitry external to chip 101. The buck controller circuitry of FIG. 2 differs from the boost converter circuitry of FIG. 1 in that the source of NMOS transistor N1 is coupled through inductor L1 to the output node (whereas in FIG. 1 the drain of transistor N1 is coupled through diode D to the output node, and inductor L is coupled between the input potential V.sub.in and the source of N1), Schottky diode D1 is connected between ground and the source of N1 (replacing diode D of FIG. 1), sense resistor R.sub.sense is connected between the input potential V.sub.in and the drain of N1 (rather than between ground and the source of N1 as in FIG. 1), and boost capacitor C.sub.B is coupled between chip 101 and the source of transistor N1.
Controller chip 101 includes elements 2, 4, 6, 8, 9 and 10 of FIG. 1 (which are connected as shown in FIG. 1, but are not shown in FIG. 2 for simplicity). Chip 101 differs from chip 1 of FIG. 1 only in minor respects apparent to those of ordinary skill in the art (including in that it has a pin coupled to boost capacitor C.sub.B). Chip 101 of FIG. 2 functions in essentially the same manner as does chip 1 of FIG. 1, including by turning on transistor N1 by setting latch 4 (in response to pulses from a clock pulse train produced by oscillator 2) and turning off transistor N1 by resetting latch 4 in response to a comparison of V.sub.c -V.sub.osc (where V.sub.osc is a ramped voltage produced by oscillator 2 and V.sub.c is the potential at the pin labeled "FB") with a feedback potential indicative of the potential V.sub.s at Node E (between resistor R.sub.sense and the drain of N1). After latch 4 within chip 101 has been set, the latch 4 resets (causing driver 6 within chip 101 to assert a potential V.sub.DR to the gate of transistor N1 which turns off transistor N1) when V.sub.s =V.sub.c -V.sub.osc .
The FIG. 2 converter is subject to the above-noted disadvantage of the FIG. 1 circuit. Specifically, because V.sub.out is typically initially much lower than its regulated value, the duty cycle of switch N1 during start up is typically initially very high FIG. 3 is graph of the potential difference between the gate of transistor N1 (which is at potential V.sub.DR) and the source of transistor N1 (which is at potential V.sub.SW) during start up of the FIG. 2 converter. It is apparent from FIG. 3 that transistor N1 initially has a high duty cycle (N1 is initially switched on for time intervals much longer than the intervals in which it is off), and that the duty cycle of transistor N1 decreases as the FIG. 2 converter settles into its equilibrium state.
As shown in FIG. 4, this situation typically causes t he current i.sub.L through inductor L1 to rise (e.g., at time T1) above its equilibrium value before it settles (e.g., at later time T2) into a value in a range of values very near its equilibrium value. Because inductor current i.sub.L cannot change instantaneously, it typically remains above its equilibrium value for a short time (as shown in FIG. 4). This causes output potential V.sub.out to rise above its regulated value (e.g. , between times T1 and T2 as shown in FIG. 5).
We shall use the expression "switching regulator" chip herein to denote a circuit which performs the functions of a "switching controller" chip (e.g., controller 1 of FIG. 1 or controller 101 of FIG. 2) but which also includes an on-board power switch. In contrast, a "switching controller" chip does not include an on-board power switch and must be used with an external power switch (as controller chip 1 of FIG. 1 is used with an NMOS transistor N1 which is external to chip 1). Switching controller chip 1 of FIG. 1 is an example of a "current mode" switching controller chip. There are other types of switching controller and regulator chips (such as voltage mode switching controllers) which can be implemented in accordance with the invention, some of which work without an external sense resistor while others require an external sense resistor.
Some conventional DC-to-DC converters differ from the conventional circuits of FIGS. 1 and 2 (and that of FIG. 6 to be discussed below) in that they include a switching regulator chip (e.g., a current mode switching regulator chip) in place of a switching controller chip. The switching regulator chip in such a converter typically does not include a sense resistor, and instead is typically used with an external sense resistor (such as resistor R.sub.s of FIG. 1). For example, one such converter employs a current mode switching regulator chip that differs from chip 1 of FIG. 1 in that counterparts to NMOS transistor N1 and resistors R.sub.f1 and R.sub.f2 are implemented on-board the regulator chip. In this type of converter, the circuitry external to the regulator chip does not include an external power switch, but it does include an external sense resistor (e.g., an external sense resistor identical to resistor R.sub.s of FIG. 1). Conventional converters which include regulator chips are also subject to the above-noted disadvantages of the circuits of FIGS. 1 and 2, unless they are implemented with soft start circuitry.
We next describe soft start circuitry of the type conventionally employed to avoid overshoot in DC-to-DC converters. FIG. 6 is a schematic diagram of a conventional DC-to-DC converter which is identical to that of FIG. 2 except in that it includes conventional soft start circuitry. The soft start circuitry comprises circuitry (to be described) within controller chip 102, and switch S.sub.1 and capacitor C.sub.soft which are external to chip 102. Chip 102 is identical to chip 101 of FIG. 2, except in that chip 102 includes soft start circuitry (including current source l.sub.soft) to be described below.
In operation of the FIG. 6 converter, at time t=0 (when the "soft start" start up operation begins), switch S.sub.1 is opened to cause capacitor C.sub.soft to start charging up at a rate of l.sub.soft /C.sub.soft. In response to the actual voltage across soft start capacitor C.sub.soft, controller chip 102 limits the duty cycle of switch N1. Initially during a soft start, controller 102 causes the duty cycle of N1 to be very low since the voltage across C.sub.soft is low. As the voltage across C.sub.soft rises, the duty cycle of N1 is allowed to increase until it reaches its equilibrium value. The capacitance of C.sub.soft is chosen so that there is minimal overshoot for a given application.
The soft start circuitry implemented as part of controller chip 102 includes current source l.sub.soft (connected to capacitor C.sub.soft as shown in FIG. 6), an OR gate, and an overvoltage comparator (not shown in FIG. 6) having an inverting input coupled to the top plate of capacitor C.sub.soft and a noninverting input coupled to receive the feedback potential V.sub.fb from Node A (between resistors R.sub.F1 and R.sub.F2) The output of the overvoltage comparator is asserted to one input of the OR gate. The other input of the OR gate receives the normal reset signal (e.g., a reset signal of the type asserted from comparator 8 of FIG. 2 to trigger the switching off of transistor N1). The circuitry is configured so that the voltage across capacitor C.sub.soft increases more rapidly than does the feedback potential V.sub.fb, so that, at the start of the start up period, the output of the overvoltage comparator is a logical "1" which forces the output of the OR gate to a level which triggers the prompt switching off of transistor N1 (promptly after each time that N1 switches on) regardless of the level of the normal reset signal. As the start up period progresses, the output of the overvoltage comparator begins to transition from a logical "0" to a logical "1" at progressively later times (relative to each event of switching on transistor N1). When the output of the overvoltage comparator is a logical "0," the output of the OR gate depends on the value of the normal reset signal (and indeed it follows the normal reset signal). As a result, the duty cycle of transistor N1 gradually increases from the start to the end of the start up period. At the end of the start up period, the voltage across capacitor C.sub.soft has become so large that the output of the overvoltage comparator remains at a logical "0," so that the output of the OR gate follows the normal reset signal.
FIG. 7 is a graph of the voltage asserted by controller chip 102 of the FIG. 6 circuit between the gate and source of NMOS transistor N1, during start up of the FIG. 6 circuit. Consistent with the foregoing description, FIG. 7 shows that the duty cycle of transistor N1 gradually increases from the start to the end of the start up period. After the end of the start up period, the duty cycle of transistor N1 is regulated in normal fashion (i.e., as it is during steady state operation of the FIG. 2 circuit) in response to the potential at Node B of FIG. 6.
FIG. 8 is a graph of the current i.sub.L through inductor L1 of FIG. 6 during the start up period, showing that the average value of this current rises gradually during start up. FIG. 9 is a graph of the output potential V.sub.out of FIG. 6 during the start up period, showing that the value of the output potential rises gradually during start up (without overshoot) from its initial value (zero) to its regulated (steady state) value.
Because the duration of the soft start operation is typically on the order of milliseconds, large capacitance values of C.sub.soft are required when using typical values of l.sub.soft (which is generated on chip 102). Such large values of C.sub.soft are too large for capacitor C.sub.soft to be implemented on-board chip 102, so that an external pin is required to connect an external C.sub.soft with the portion of the soft start circuitry which is on-board chip 102. This is a disadvantage since in some applications, it is not practical (or it is undesirable) to implement a controller (or regulator) chip with an extra external pin for connection to a soft start capacitor.
In some conventional current mode switching controllers, an external compensation capacitor (corresponding to capacitor C.sub.c of FIGS. 2 and 6, which is coupled to chip 101 or 102 at the pin labeled "COMP") is employed for two functions: it performs its normal compensation function; and it also functions as a soft start capacitor. This eliminates the need for a separate external soft start capacitor (and an additional external pin for coupling the chip to a separate external soft start capacitor), but it has the disadvantage of making optimization of the dual function capacitor value difficult or impossible, since a trade off in the capacitance value will typically be required to satisfy all of the compensation, overshoot, and transient response requirements.